OpenASIC
    • \[\[global:header.categories\]\]
    • \[\[global:header.recent\]\]
    • \[\[global:header.tags\]\]
    • \[\[global:header.popular\]\]
    • \[\[global:header.users\]\]
    • \[\[global:header.groups\]\]
    • \[\[global:header.search\]\]
    • Register
    • Login

    首款开源H.265 Video Encoder IP Core发布

    Scheduled Pinned Locked Moved 新闻文档 | News & Documents
    h.265
    28 Posts 14 Posters 259.3k Views
    Loading More Posts
    • Oldest to Newest
    • Newest to Oldest
    • Most Votes
    Reply
    • Reply as topic
    Log in to reply
    This topic has been deleted. Only users with topic management privileges can see it.
    • B Offline
      bo @zhuzhuqing0
      last edited by

      @zhuzhuqing0 C Model 后期我会出个软件给大家，方便大家使用。

      F 1 Reply Last reply Reply Quote 0
      • B Offline
        bo @maurice
        last edited by

        @maurice Pure HW， written by Verilog HDL (RTL)

        1 Reply Last reply Reply Quote 0
        • B Offline
          bo @yx9527
          last edited by

          @yx9527 后面出个参考软件给大家，自己跑吧 😃
          说实话，目前曲线上结果不是太好，别期望太高哦。正在进一步改进中

          1 Reply Last reply Reply Quote 0
          • F Offline
            fighting @bo
            last edited by

            @bo 范老师，C Model大概什么时候发布？会发布源代码吗？

            B 1 Reply Last reply Reply Quote 0
            • B Offline
              bo @fighting
              last edited by

              @fighting C Model暂时不开放源代码，会对参与项目开发的人员开放代码。一般用户其实只需要RTL就够了

              1 Reply Last reply Reply Quote 0
              • K Offline
                kelly
                last edited by

                范老师，您好！ 我一部分工作是作视频处理算法的，从事IC设计有十余载，希望有机会可以参与贵团队的工作，无论编码、设计、架构、优化都可以。 真的非常高兴国内有越来越多这样的共创平台。

                B L 2 Replies Last reply Reply Quote 0
                • K Offline
                  kelly
                  last edited by

                  我用synopsys － DVE （or say VCS） 将仿真跑起来了，目前run 正常无报错

                  Chronologic VCS simulator copyright 1991-2014
                  Contains Synopsys proprietary information.
                  Compiler version I-2014.03-2_Full64; Runtime version I-2014.03-2_Full64; Dec 26 15:02 2016
                  ucli% run

                  *** CHECK TOP ! ***

                               fime auto check is on
             fme auto check is on
             mvd auto check is on
             db auto check is on
             fetch auto check is on
             bs auto check is on

                  *** TEST P FRAMES ! ***

                      at 00000600, Frame Number = 00, mb_x_first = 00, mb_y_first = 00
    at 00050065, Frame Number = 00, mb_x_first = 01, mb_y_first = 00
    at 00091015, Frame Number = 00, mb_x_first = 02, mb_y_first = 00
    at 00131965, Frame Number = 00, mb_x_first = 03, mb_y_first = 00
    at 00172915, Frame Number = 00, mb_x_first = 04, mb_y_first = 00
    at 00213865, Frame Number = 00, mb_x_first = 05, mb_y_first = 00
    at 00273695, Frame Number = 00, mb_x_first = 06, mb_y_first = 00
    at 00314645, Frame Number = 00, mb_x_first = 00, mb_y_first = 01
    at 00355595, Frame Number = 00, mb_x_first = 01, mb_y_first = 01
    at 00396545, Frame Number = 00, mb_x_first = 02, mb_y_first = 01
    at 00437495, Frame Number = 00, mb_x_first = 03, mb_y_first = 01
    at 00478445, Frame Number = 00, mb_x_first = 04, mb_y_first = 01
    at 00519395, Frame Number = 00, mb_x_first = 05, mb_y_first = 01
                  1 Reply Last reply Reply Quote 0
                  • B Offline
                    bo @kelly
                    last edited by

                    @kelly 赞！

                    1 Reply Last reply Reply Quote 0
                    • K Offline
                      kelly
                      last edited by

                      范老师, 如果真想拿个asic SoC 项目把这个VENC 集成进去
                      －－这其实也是件很快的事情，因为我本来就有这样的SoC项目，用的是verisillicon的h.265；
                      跑一跑SoC的top仿真，
                      以及放到emulator上也就是用FPGA搭建的emulation的环境上跑跑的话，
                      还是需要更多测试例的，如果能开放相应的C model就好了，
                      我可以将C model 修改得更接近UVM平台 得架构， 对关键模块及节点进行自动化实时数据对比。
                      我真的非常急切渴望知道和确定RTL代码的实际可用性！

                      1 Reply Last reply Reply Quote 0
                      • K Offline
                        kelly
                        last edited by

                        或者，范老师，不知道是否方便联系您？

                        B 1 Reply Last reply Reply Quote 0
                        • B Offline
                          bo @kelly
                          last edited by

                          @kelly 请联系我吧。 我email: fanyibo@fudan.edu.cn

                          1 Reply Last reply Reply Quote 0
                          • W Offline
                            wlf8263121
                            last edited by

                            @bo ，can you share cmodel or x265,which we can compare your encoder performance with others!

                            1 Reply Last reply Reply Quote 0
                            • X Offline
                              xuelijun
                              last edited by

                              范老师，为何下载总显示："not-allowed"

                              B 1 Reply Last reply Reply Quote 0
                              • B Offline
                                bo @xuelijun
                                last edited by

                                @xuelijun 你要先注册后下载的

                                1 Reply Last reply Reply Quote 0
                                • P Offline
                                  paulhwang
                                  last edited by

                                  范教授您好，我是一名视频编解码的学习者，想问下您能否提供一份这个Encoder IP CORE的说明文档呢？

                                  1 Reply Last reply Reply Quote 0
                                  • L Offline
                                    liunan @kelly
                                    last edited by

                                    @kelly 你好 方便留个联系方式吗

                                    B 1 Reply Last reply Reply Quote 0
                                    • B Offline
                                      bo @liunan
                                      last edited by

                                      @liunan 我的email fanyibo@fudan.edu.cn

                                      1 Reply Last reply Reply Quote 0
                                      • B Offline
                                        bytree1
                                        last edited by

                                        你好范老师。
                                        我下载代码在vcs下仿真通过。但有几个问题请教下。
                                        1.看top.v中，cabac模块的sao_in直接接0，等于说自带平台不支持sao。如果想支持的，如何修改？
                                        2.sao是否只支持band，没有edge？
                                        3.我尝试修改enc_define的LCU大小，从64变成32，但是编译时发现，不少代码还是按64的大小编写的，直接编译会报out of boundary。
                                        4.你们是否有帧压缩的内容？

                                        谢谢！

                                        B 1 Reply Last reply Reply Quote 0
                                        • B Offline
                                          bo @bytree1
                                          last edited by

                                          @bytree1 目前sao没支持edge， LCU只能是64的 32的没支持，帧压缩没支持

                                          1 Reply Last reply Reply Quote 0
                                          • 1
                                          • 2
                                          • 1 / 2
                                          • First post
                                            Last post
                                          Copyright © 2016 OpenASIC.XinKai
                                          VIP Lab @Fudan University | XK Silicon