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bo， 该方案中，1080p视频源从PYNQ板载HDMI输入，经H.264编码后，码流从以太网发送，另一台PC机接受码流并用VLC解码。
受限于FPGA开发板性能，该演示方案H.264 IP Core仅运行在30MHz频率，实时1080p编码的帧率在10fps左右。
请问一下，受限于FPGA开发板的的性能，是DDR带宽限制，还是其他方面？