Posts made by eebq
H.264 decoder IP Core RTL Code (v1.0)
Model Osen Logic OSD10 h.264 decoder
Input Format H.264 NAL stream
Output Format YUV4:2:0
Slice type supported I,SI,P,SP
Entropy Coding CAVLC
Supported frme size Max: 1920x1088,Min:640x480
Supported bitrate 0 to 10Mps,No decode rate control
Max resolution and frame rate 1920x1088 @ 30fps, working at 75M
Required external memory size 32Mbyte
Memory interface data width 64bit
请问我能发布我的h.264 decoder RTL及testbench在这里吗
大学和毕业后我做了一个h.264 decoder， 现在已应用在无人机的工程里，现在我想公开一个不带deblock的版本在这里, deblock版本不开源， deblock一个宏块只需50多个时钟，和其他过程可以同步进行，所以基本不影响解码速度。
♦ The Osen Loigc OSD10 core is a hardware implementation of the H.264
baseline video compression algorithm.
It is Simple, fully synchronous design with low operating freqency.
♦ Supports up to the highest HDTV video resolution (1920x1080 @
30 fps progressive) on FPGA.
♦ Simple, fully synchronous design.
♦ Single core HDTV support in FPGA : 720p (1280x720) at 60 fps or
1080p(1920x1080) at 30fps in High end FPGAs (Zynq7020 lowest speed grade).
♦ Fast Deblocking Filter:Only 60 Clocks are needed to deblock a 16x16 block.
♦ No CPU required for decoding.
♦ Very low latency decoding
♦ Any Motion vector is supported.
♦ Support for all of intra4x4 and all intra16x16 modes except IPCM.
♦ Multiple slices supported.
♦ Deblocking filter for better quality.
♦ External memory interface tolerant of high latencies and delays,
ideal in a SoC system or in a shared bus with a CPU. The memory
interface can be clocked at a different frequency from the core for
♦ Supports YUV 4:2:0 video output.
♦ Min Clock speed = about 1.4 x the raw pixel clock speed.
♦ Very low operational frequency : from 15 MHz for VGA @ 30
fps to ~75 MHz for 1920x1080 @ 30 fps.
♦ Available as synthesizable Verilog Netlist.