<![CDATA[请问我能发布我的h.264 decoder RTL及testbench在这里吗]]>大学和毕业后我做了一个h.264 decoder， 现在已应用在无人机的工程里，现在我想公开一个不带deblock的版本在这里, deblock版本不开源， deblock一个宏块只需50多个时钟，和其他过程可以同步进行，所以基本不影响解码速度。
General Description
Features
♦ The Osen Loigc OSD10 core is a hardware implementation of the H.264
baseline video compression algorithm.
It is Simple, fully synchronous design with low operating freqency.
♦ Supports up to the highest HDTV video resolution (1920x1080 @
30 fps progressive) on FPGA.
♦ Simple, fully synchronous design.
♦ Single core HDTV support in FPGA : 720p (1280x720) at 60 fps or
1080p(1920x1080) at 30fps in High end FPGAs (Zynq7020 lowest speed grade).
♦ Fast Deblocking Filter:Only 60 Clocks are needed to deblock a 16x16 block.
♦ No CPU required for decoding.
♦ Very low latency decoding
♦ Any Motion vector is supported.
♦ Support for all of intra4x4 and all intra16x16 modes except IPCM.
♦ Multiple slices supported.
♦ Deblocking filter for better quality.
♦ External memory interface tolerant of high latencies and delays,
ideal in a SoC system or in a shared bus with a CPU. The memory
interface can be clocked at a different frequency from the core for
easier integration.
♦ Supports YUV 4:2:0 video output.
♦ Min Clock speed = about 1.4 x the raw pixel clock speed.
♦ Very low operational frequency : from 15 MHz for VGA @ 30
fps to ~75 MHz for 1920x1080 @ 30 fps.
♦ Available as synthesizable Verilog Netlist.

说明如下：
[0_1496925861235_Osenlogic_OSD10_datasheet.docx](Uploading 100%)

]]>http://www.openasic.org/topic/47/请问我能发布我的h-264-decoder-rtl及testbench在这里吗RSS for NodeSat, 07 Mar 2026 05:18:39 GMTThu, 08 Jun 2017 12:47:55 GMT60<![CDATA[Reply to 请问我能发布我的h.264 decoder RTL及testbench在这里吗 on Wed, 22 Jan 2025 11:36:58 GMT]]>大佬您好，请问H264的Encoder有没有开源的C model？

]]>http://www.openasic.org/post/686http://www.openasic.org/post/686Wed, 22 Jan 2025 11:36:58 GMT<![CDATA[Reply to 请问我能发布我的h.264 decoder RTL及testbench在这里吗 on Fri, 09 Jun 2017 08:02:36 GMT]]>@bo
可能是文件格式不对7z上传了不能显示，zip和pdf可以

]]>http://www.openasic.org/post/225http://www.openasic.org/post/225Fri, 09 Jun 2017 08:02:36 GMT<![CDATA[Reply to 请问我能发布我的h.264 decoder RTL及testbench在这里吗 on Fri, 09 Jun 2017 06:54:38 GMT]]>@bo demo video 1080p
http://pan.baidu.com/s/1hswwUES

]]>http://www.openasic.org/post/223http://www.openasic.org/post/223Fri, 09 Jun 2017 06:54:38 GMT<![CDATA[Reply to 请问我能发布我的h.264 decoder RTL及testbench在这里吗 on Fri, 09 Jun 2017 06:16:23 GMT]]>@bo 范老师你好， 论坛的附件上传显示100%, 但是好像不能下载， 我先传到网盘吧，里面有C Model， RTL Code， modelsim 写入二进制文件的源码及dll文件， ascii转binary的软件。下载地址发站内信给你了。

]]>http://www.openasic.org/post/222http://www.openasic.org/post/222Fri, 09 Jun 2017 06:16:23 GMT<![CDATA[Reply to 请问我能发布我的h.264 decoder RTL及testbench在这里吗 on Thu, 08 Jun 2017 14:53:24 GMT]]>@eebq 你先建两个帖子， 一个是RTL的， 一个是Cmodel的， 我随后把这两个帖子放到代码发布下面

]]>http://www.openasic.org/post/219http://www.openasic.org/post/219Thu, 08 Jun 2017 14:53:24 GMT<![CDATA[Reply to 请问我能发布我的h.264 decoder RTL及testbench在这里吗 on Thu, 08 Jun 2017 14:51:08 GMT]]>@eebq 赞！ 欢迎发布， 你先放上来。我稍后把帖子挪到代码发布里面。

]]>http://www.openasic.org/post/217http://www.openasic.org/post/217Thu, 08 Jun 2017 14:51:08 GMT<![CDATA[Reply to 请问我能发布我的h.264 decoder RTL及testbench在这里吗 on Thu, 08 Jun 2017 13:46:31 GMT]]>我也提供baseline的c model，解码后的yuv和JM86或ffmepg对比是bit-to-bit正确的。我的testbench也生成yuv.txt，用hex2bin转为yuv二进制文件后， 可以和软件模型对比， 也是bit to bit对应的。

]]>http://www.openasic.org/post/216http://www.openasic.org/post/216Thu, 08 Jun 2017 13:46:31 GMT